The present invention relates to a high voltage semiconductor device, and particularly to a high voltage semiconductor device including an insulated gate bipolar transistor (IGBT).
In recent years, research and development have been eagerly conducted on a technique for forming both a high voltage semiconductor device and a peripheral driving circuit for driving the device on the same substrate. The technique allows the whole system to be compact or highly integrated and to decrease its manufacturing cost.
There is a known method of fabricating a semiconductor device, using a silicon layer adhered to a substrate through an insulating film, i.e., silicon on an insulator (SOI), in order to achieve a high breakdown voltage. With this technique, the insulating film shears a loaded voltage, thereby improving its breakdown voltage. Further, with this technique, a high voltage semiconductor device and a low voltage peripheral driving circuit can be arranged on a substrate and separated by a trench. In other words, the high voltage semiconductor device and the peripheral driving circuit can be arranged on the same substrate, thereby allowing the whole system to be compact and inexpensive.
High voltage semiconductor devices should perform a high current output and a low loss output. In light of the high current output, it is preferable for the devices to be of the bipolar type. However, in light of controllability, since peripheral driving circuits perform a voltage output, it is preferable for the devices to be of the MOS type. IGBTs are known as -one type of high voltage semiconductor device, which satisfy the above two points. FIG. 13 is a cross-sectional view showing a structure of a conventional lateral IGBT.
This device has a silicon substrate 70 having a surface covered with an oxide film 81. An n-base layer 74 having a high resistance is formed on the oxide film 81, and a p-base layer 79 is formed in a surface of the n-base layer 74.
In a surface of the p-base layer 79, an n-source layer 78 having a low resistance, and a p-contact layer 77 having a low resistance and arranged in contact with the n-source layer 78, are formed. A source electrode 76 is arranged in contact with the n-source layer 78 and the p-contact layer 77.
A gate electrode 76 is arranged through a gate insulating film 80 on the p-base layer 79 between the n-source layer 78 and the n-base layer 74. A gate electrode 75 is provided with a stepped portion, as shown in FIG. 13, such that the electrode 75 functions as a field plate.
An n-buffer layer 72 is formed in the surface of the n-base layer 74, and separated from the p-base 5 layer 79 by a certain distance. A p-drain layer 73 having a low resistance is formed in a surface of the n-buffer layer 72. A drain electrode 82 is arranged in contact with the p-drain layer 73.
When the lateral IGBT described above is turned on, the gate electrode 75 is supplied with a gate voltage, which is positive to the source electrode 76 and is higher than a threshold voltage. When such a gate voltage is applied to the gate electrode 75, an n-channel is formed in the surface of the p-base layer 79 under the gate insulating film 80, and electrons are injected from the n-source layer 78 into the n-base layer 74 through the n-channel.
With the injection of electrons into the n-base layer 74, holes are injected from the p-drain layer 73 into the n-base layer 74 through the n-buffer layer 72. As a result, electrons and holes are accumulated in the n-base layer 74 and cause conductivity modulation, thereby decreasing the resistance of the n-base layer 74. It follows that the main electric current, i.e., drain current, comes to flow, while ON-resistance is kept low, and the device is turned on.
On the other hand, when the device is turned on, a gate electrode 75 is supplied with a gate voltage less than the threshold voltage. When such a gate voltage is applied to the gate electrode 75, the n-channel in the surface of the p-base layer 79 disappears, and electrons stop being injected from the n-source layer 78 into the n-base layer 74. Holes remaining in the n-source layer 78 are exhausted through the p-base layer 79 and the p-contact layer 77 to the source electrode 76. As a result, the main electric current becomes zero, and the device is turned off.
However, the above described IGBT has the following problems.
In an ON-state, a difference is brought about between a voltage drop caused by a hole current laterally flowing in the p-base layer 79 and a voltage drop caused by an electron current laterally flowing in the n-source layer 78. Due to this voltage difference, a p-n junction formed by the p-base layer 79 and n-source layer 78 or by the p-contact layer 77 and n-source layer 78 is forward-biased. When the forward bias becomes larger than the built-in voltage of the p-n junction, a parasitic transistor is turned on. In this case, a latch-up occurs and makes it impossible to turn off the device by a gate voltage for causing the main current to be zero. Further, such a lateral IGBT formed on an SOI substrate entails a problem in that it is apt to break down when driven with no load, i.e., its short-circuit withstand capability is low.